1. Field of the Invention
The present invention relates to a fabricating method of a thin film transistor substrate. More particularly the present invention relates to a fabricating method of a thin film transistor substrate that is adaptive for forming a good pattern design and removing a stepped difference at the same time using a three-mask process.
2. Description of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal by use of an applied electric field, thereby displaying a picture. The liquid crystal display device drives the liquid crystal by the electric field formed between a common electrode and a pixel electrode which are disposed to face each other in upper and lower substrates.
The liquid crystal display device includes a thin film transistor substrate and a color filter substrate which are bonded to face each other; a spacer for fixedly keeping a cell gap between two substrates; and a liquid crystal filled in the cell gap.
The thin film transistor substrate includes a plurality of signal lines, thin film transistors and an alignment film which is spread thereon for aligning liquid crystal. A color filter array substrate includes a color filter for realizing color; a black matrix for preventing light leakage; and an alignment film which is spread thereon for aligning liquid crystal.
In such a liquid crystal display device, a thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes. Thus, the fabrication process is complicated and is a major factor for the increased fabrication costs of the liquid crystal panel.
In order to solve the problem as described above, the thin film transistor substrate is developed in a direction of reducing the number of mask processes. One mask process includes a lot of sub-processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo-resist peeling process, an inspection process, etc.
Accordingly, use of a three-mask process has recently been on the rise, wherein the three-mask process uses a lift-off method or passiless method by which one mask process can be reduced from a five mask or four mask process which was a standard mask process of the thin film transistor substrate.
In reference to FIGS. 1 and 2, the structure and operation of the thin film transistor substrate which is fabricated by the related art three-mask process will be explained.
Referring to FIGS. 1 and 2, a thin film transistor substrate fabricated by the related art three-mask process includes a gate line 20 formed on a substrate 10; a data line 30 which crosses the gate line 20 with a gate insulating film 25 therebetween to define a pixel area 61; a thin film transistor 40 formed at each crossing part thereof; a pixel electrode 60 formed at the pixel area 61 to be connected to the thin film transistor 40; a storage capacitor 70 formed at an overlapping part of the gate line 20 and the storage electrode 65; a gate pad 80 connected to the gate line 20; and a data pad 90 connected to the data line 30.
Herein, the thin film transistor 40 acts to charge the pixel electrode 60 with a pixel signal of the data line 30 in response to a gate signal of the gate line 20, and includes a gate electrode 22 connected to the gate line 20, a source electrode 32 connected to the data line 30 and a drain electrode 33 which faces the source electrode 32 with a channel therebetween and has its side connected to the pixel electrode 60.
Herein, the thin film transistor 40 further includes an active layer 34 which is formed to overlap the gate electrode 22 with a gate insulating film 25 therebetween to form a channel between the source electrode 32 and the drain electrode 33, and an ohmic contact layer 35 formed on the active layer 34 except a channel part for making the active layer 34 in ohmic contact with the source electrode 32 and the drain electrode 33.
At this moment, the active layer 34 and the ohmic contact layer 35 are formed to overlap the data line 30, a data pad lower electrode 91 and a storage electrode 65.
A passivation film 50 covers the thin film transistor 40 formed on a gate insulating film 25 and acts to protect the active layer 34 which forms the channel from moisture or a scratch which might be generated in the following process.
The pixel electrode 60 is formed in a pixel hole 61 of a pixel area defined by the crossing of the gate line 20 and the data line 30, and the pixel electrode 60 is formed to make a boundary with the passivation film 50 while being in side-contact with the drain electrode 33 of the thin film transistor 40.
More specifically, the pixel electrode 60 is side-connected to the drain electrode 33 which is partially etched when forming the pixel hole 62 that penetrates the passivation film 50 and the gate insulating film 25, and is formed to overlap a part of the active layer which is exposed by the etched drain electrode 33 or to be in side-contact with the gate insulating film 25.
An electric field is formed between the pixel electrode 60 to which the pixel signal is supplied through the thin film transistor 40 and a common electrode (not shown) to which a reference voltage supplied.
Accordingly, the electric field formed between the pixel electrode 60 and the common electrode rotates liquid crystal molecules filled between the thin film transistor substrate and the color filter substrate by a dielectric anisotropy, and makes the transmittance of the light transmitted through the pixel area changed in accordance with the rotation degree of the liquid crystal molecules, thereby realizing the gray level.
The storage capacitor 70 includes the gate line 20, and a storage electrode 65 which overlaps the gate line 20 with the gate insulating film 25, the active layer 34 and the ohmic contact layer 35 therebetween. Herein, the pixel electrode 60 formed to make a boundary with the passivation film 50 within the pixel hole 61 is connected to the side of the storage electrode 65. The storage capacitor 70 makes the pixel signal which is charged in the pixel electrode stably kept until the next pixel signal is charged.
The gate pad 80 is connected to a gate driver (not shown) to supply the gate signal to the gate line 20. The gate pad 80 includes a gate pad lower electrode 81 extended from the gate line 20, and a gate pad upper electrode 82 which is connected to the gate pad lower electrode 81 through the inner surface of a first contact hole 51 that penetrates the gate insulating film 25 and the passivation film 50.
The data pad 90 is connected to the data driver (not shown) to supply a data signal to the data line 30. The data pad 90 includes a data pad lower electrode 91 extended from the data line 30, and a data pad upper electrode 92 which is connected to the data pad lower electrode 91 through the inner surface of a second contact hole 53 that penetrates the passivation film 50.
At this moment, the data pad upper electrode 92 is in contact with the gate insulating film 25 or with the remaining active layer 34 as the ohmic contact layer 35 and the active layer 34 which constitute the data pad lower electrode 91 are etched when forming the second contact hole 52.
Hereinafter, a method of fabricating a thin film transistor substrate using a related art three-mask process will be described in detail with reference to the FIG. 3A to 3L.
First, a first conductive pattern including a gate line 20, a gate electrode 22 and a lower gate pad electrode 81 are formed on a lower substrate 10 using a first mask process, as shown in FIG. 3A.
More specifically, a gate metal layer is formed on the lower substrate 10 by a deposition technique such as a sputtering, etc.
A photo-resist is spread over the entire surface of the gate metal layer, a photolithography process using a first mask is performed, thereby forming a first conductive pattern inclusive of the gate line 20, the gate electrode 22 connected to the gate line and the gate pad lower electrode 81 on a lower substrate 10.
As described above, after forming the first conductive pattern on the lower substrate 10, a second conductive pattern and a semiconductor pattern forming a channel are formed on the gate insulating film 25 by a second mask process.
To describe this more specifically, as shown in FIG. 3B, the gate insulating film 25, an amorphous silicon layer 34A, an n+ amorphous silicon layer 35A and a data metal layer 30A are sequentially formed by a deposition method such as PECVD, sputtering, etc on the lower substrate 10 where the first conductive pattern is formed.
Herein, the metal forming the data metal layer 30A is a metal that can be etched together with an exposed part when etching the passivation film 50 in the following process, e.g., Mo, Cu group, Al group, Cr group, etc which can be dry-etched.
Then, after the photo-resist is spread over the entire surface of the data metal layer 30A, the photolithography process using a second mask being a diffractive exposure mask is performed, thereby forming a photo-resist pattern PR having a stepped difference on the data metal layer 30A, as shown in FIG. 3C.
A halftone mask of which a diffractive exposure part corresponds to a channel area of the thin film transistor 40 is used as the second mask, thus the photo-resist pattern formed in the channel area is formed to have lower height than the photo-resist pattern formed in the other area.
As described above, after forming the photo-resist pattern having a deviation on the data metal layer 30A, the data metal layer 30A exposed by the photo-resist pattern is removed by a wet etching, as shown in FIG. 3D.
Then, the amorphous silicon layer 34A and the n+ amorphous silicon layer 35A exposed as the data metal layer 30A is removed by the wet etching are sequentially removed by the dry etching.
As described above, after sequentially removing the n+ amorphous silicon layer 35A and the amorphous silicon layer 34A, the photo-resist pattern is removed by an ashing process using oxygen O2 plasma, thereby exposing the data metal layer 30A formed in the channel area, as shown in FIG. 3E.
The data metal layer 30A formed in the shielding area is also exposed as the photo-resist pattern corresponding to the shielding part of the diffractive exposure mask is removed by the ashing process using the oxygen O2 plasma.
Then, the data metal layer 31 exposed in the channel area and the shielding area is removed by the dry etching, thereby forming the data line 30, the source electrode 32 connected to the data line 30, the drain electrode which faces and is separated from the source electrode 32, the data pad lower electrode 91 and the storage electrode 65, as shown in FIG. 3F.
The storage electrode 65 is formed to overlap the gate line 20 with the gate insulating film 25 and the semiconductor pattern therebetween, and the n+ amorphous silicon layer 35A formed in the channel area is opened as the source electrode 32 is separated from the drain electrode 33.
As described above, the n+ amorphous silicon layer 35A opened in the channel area is removed by the dry etching, thereby sequentially forming the active layer 34 and the ohmic contact layer which form a channel of the thin film transistor 40, as shown in FIG. 3G.
Then, the photo-resist pattern remaining on the gate insulating film 25 is removed, thereby forming the semiconductor pattern inclusive of the ohmic contact layer 35 and the active layer 34 for forming the channel; and the second conductive pattern inclusive of the data line 30, the source electrode 32 connected to the data line 30, the drain electrode 33 which corresponds to the source electrode 32 with the channel therebetween, the storage electrode 65 and the data pad lower electrode 91, as shown in FIG. 3H.
As described above, after forming the semiconductor pattern and the second conductive pattern on the gate insulating film 25, the passivation film 50 and a third conductive pattern are formed on the gate insulating film 25 by the lift-off process using a third mask.
To describe this more specifically, after depositing the passivation film 50 on the entire surface of the gate insulating film 25 where the semiconductor pattern and the second conductive pattern are formed, the photolithography process using the third mask is performed, thereby forming a photo-resist pattern which is for forming first and second contact holes 51, 52 and the pixel hole 61 on the passivation film 50, as shown in FIG. 31.
As described above, after forming the photo-resist pattern on the passivation film 50, the gate insulating film 25 and the passivation film 50 exposed by the photo-resist pattern are sequentially removed by the dry etching, thereby forming the first and second contact holes 51, 52 and the pixel hole 61 where the pixel electrode is to be deposited, as shown in FIG. 3J.
The first contact hole 51 penetrates the passivation film 50 and the gate insulating film 25 to expose the gate pad lower electrode 81, and the second contact hole 52 penetrates the passivation film 25 to expose the data pad lower electrode 91.
And the pixel hole 61 penetrates the passivation film 50 and the gate insulating film 25 formed in the pixel area 60 to expose the lower substrate 10. At this moment, the active layer 34 and the ohmic contact layer 35 overlapped with the drain electrode 33 are sequentially etched as the side of the drain electrode exposed when the dry etching for forming the pixel hole 62 is performed is etched.
As described above, after forming the first and second contact holes 51, 52 and the pixel hole 61 on the passivation film 50 by use of the photo-resist pattern, a transparent conductive film 60A is deposited on the entire surface of the lower substrate 10 where the photo-resist pattern is formed by use of the sputtering method, etc, as shown in FIG. 3K.
At this moment, an undercut area ‘A’ is generated between the transparent conductive film 60A formed on the passivation film 50 and the transparent conductive film 60B formed in the pixel hole 61 area.
Then, after removing the photo-resist pattern formed on the passivation film 50 by the etching process using the undercut area ‘A’, the transparent conductive film 60A formed on the photo-resist pattern by the lift-off process is removed, thereby forming the third conductive pattern inclusive of the pixel electrode 60, the gate pad upper electrode 82, the data pad upper electrode 92, as shown in FIG. 3L.
At this moment, the pixel electrode 60 is formed to make a boundary with the passivation film 50 within the pixel hole 61 and is connected to the side of the drain electrode 33.
And, the gate pad upper electrode 82 forms a side boundary with the gate insulating film 25 and the passivation film 50 which are patterned within the first contact hole 51, and the gate pad upper electrode 82 is connected to the gate pad lower electrode 81.
Further, the data pad upper electrode 92 forms a boundary with the passivation film 50 within the second contact hole 52 and is side-connected to the data pad lower electrode 92.
As described above, in a case of fabricating the thin film transistor substrate by the lift-off process using the third mask, there is a problem in that an area ‘B’ where no undercut is generated is formed as the transparent conductive film 60A formed on the passivation film 50 and the transparent conductive film 60B formed in the pixel hole 61 are short-circuited, as shown in FIG. 4.
Further, in a case in which impurities are present while the transparent conductive film 60A is formed on the passivation film 50 and the transparent conductive film 60B formed in the pixel hole 61 are short-circuited, an etching solution for stripping the photo-resist pattern permeates along the path through which the impurities are present, thus there is a problem that there is generated an area ‘C’ where a part of the transparent conductive film 60B formed in the pixel hole 61 is lost, as shown in FIG. 5.